
`include "defines.v"

module regfile(
	input  wire clk,
	//READ PORT 1
	input  wire [ 4:0] raddr1,
	output wire [63:0] rdata1,
	//READ PORT 2
	input  wire [ 4:0] raddr2,
	output wire [63:0] rdata2,
	//WRITE PORT
	input  wire 	   we    ,
	input  wire [ 4:0] waddr ,
	input  wire [63:0] wdata ,

	output wire [63:0] regs_o[0: 31]      //difftest    
	);

reg [63:0] rf[31:0];  //64 Bit length, 32 Registers

integer i = 0;
initial begin
	for(i = 0; i<32; i = i + 1) begin
		rf[i] = 0;
	end
end

//READ OUT 1
assign rdata1 = (raddr1==5'b0) ? 64'b0 : rf[raddr1];

//READ OUT 2
assign rdata2 = (raddr2==5'b0) ? 64'b0 : rf[raddr2];

//WRITE
always @(posedge clk) begin
	if(we && (waddr != 5'd0)) rf[waddr] <= wdata;
end

genvar j;
generate
	for(j = 0; j<32; j=j+1) begin
	  assign regs_o[j] = (we & waddr == j & j != 0) ? wdata : rf[j];
	end
	
endgenerate



endmodule
